Search Results for "hdl"
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Showing 62 open source projects for "hdl"
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FuseSoC
Package manager and build abstraction tool for FPGA/ASIC development
FuseSoC is a package manager and build abstraction tool for hardware description language (HDL) code, aimed at simplifying the development and reuse of IP cores. It provides a standardized way to describe, manage, and build hardware projects, facilitating collaboration and reducing duplication of effort in FPGA and ASIC development. -
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SpinalHDL
Scala based HDL
SpinalHDL is a hardware description (HDL) framework embedded in Scala, enabling hardware designers to build digital circuits with modern programming abstractions. Instead of writing in Verilog or VHDL directly, users describe hardware components and their interconnects using Scala code and Spinal’s domain-specific library, which then emits synthesizable hardware (e.g. as Verilog). -
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. ... -
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When the first computer was invented , computers change the world. The revolution oriented from digital circuit design makes human society running faster and faster. The patent rights of digital circuit are very important properties to make fortune in commercial market. 電腦及數位科技造就第四次工業革命，高價值數位電路設計代表高科技與高利潤，所以數位電路設計成為各國專利權攻防的焦點目標 數位電路架構受專利法及著作權法保護， 請勿使用本程式模擬他人合法申請專利之數位電路架構， 本人不同意使用本程式之商業行為 The patent right of digital circuit design could possibly be under the protection of...
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Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at https://github.com/kactus2/kactus2dev/issues For publications, kindly use this reference: http://joss.theoj.org/papers/73e33d6850d24f0d6aad0d5f38937f83 Contributors: Antti Kamppi, Joni-Matti Määttä, Lauri Matilainen, Timo D. ... -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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XSCHEM
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So, the interface developed acts as a front-end that allows writing code (with syntax highlighting), invokes an external VHDL compiler and simulator (such as GHDL), and displays the result of the simulation graphically as waveforms (invoking to GTKWave). -
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We provide an open-source library of approximate recursive multipliers described using Verilog HDL. In case of usage please refer to: H. Waris, C. Wang, C. Xu and W. Liu, "AxRMs: Approximate Recursive Multipliers using High-Performance Building Blocks," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2021.3096515.
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We provide an open-source library of approximate arithmetic modules (adders and multipliers) described using Verilog HDL. In case of usage please refer to: H. Waris, C. Wang, W. Liu, J. Han and F. Lombardi, "Hybrid Partial Product-based High-Performance Approximate Recursive Multipliers," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2020.3013977.
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Approximate Solution Finder
An open-source approximate logic design tool
We provide an open-source library of approximate multipliers described using Verilog HDL. The article related to the library is currently under review. -
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HDL Checker
Repurposing existing HDL tools to help writing better code
HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer the library VHDL files likely to belong to, besides working out mixed language dependencies, compilation order, interpreting some compiler messages and providing some (limited) static checks. -
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ABSYNTH
ABSYNTH a generator of microprogram control units in HDL
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Integrated Circuit Design Software that quickly automates design of analog and digital circuits for use in schematics, device modelling, design re-use, architecture, signal processing and IC manufacture.
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scFvMiner
Scripts for analysing NGS data
...The methods are descriped in Lövgen, J., Pursiheimo, J.P., Pyykkö, M., Salmi, J. & Lamminmäki, U. (2016) Next generation sequencing of all variable loops of synthetic single framework scFv – application in anti-HDL antibody selections. New Biotechnology 33:790-796. -
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Emulator of EPOS-73
The behavioral model of the old Soviet calculator EPOS-73
This project introduces a console application designed for functional and behavioral emulation of the old Soviet calculator EPOS-73 (ЭПОС-73) also known as Elektronika B3-11 (Электроника Б3-11). The project is conceived as an auxiliary for verification of the switch-level simulator based on Verilog HDL of the said apparatus. Calculator model EPOS-73 is interesting in that it was one of the first models of Soviet computing performed at LSI, that were fully designed by Soviet engineers. It was used a set of four LSIs series K1ZHG451...4 (К1ЖГ451...4) or later designation K145HK1...4 (К145ХК1...4). The choice of this calculator as an object of modeling is due to the presence of (miraculously survived to this day) a sufficient set of design documentation for the technology applied in its LSIs, including a technical description of the device, revealing its calculating algorithms. ... -
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THIS SITE IS NO LONGER ACTIVELY MAINTAINED, FOR RECENT RELEASES, PLEASE GO TO: http://synthesijer.github.io/web/dl/ For more information, please go to: http://synthesijer.github.io/web/ Synthesijer is a high-level synthesis tool, which generates HDL files from Java code. Synthesijer also provides a backend to generate VHDL/Verilog HDL, which helps to develop high-level synthesis tools and DSLs.
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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vHDL Obfuscator GUI
vHDL Obfuscator is an small GUI to obfuscate and reformat HDL files
VHDL and Verilog HDL are standards languages for hardware description. Sometimes is necessary to share the source HDL file but maintaining a little level of control and protection of the intellectual property. This tool generate obfuscated code that is almost unreadable to humans, but is still readable to compilers and simulators. This tool use GHDL (https://sourceforge.net/projects/ghdl-updates/), HDLObf (https://sourceforge.net/projects/hdlobf/), Icarus Verilog (https://sourceforge.net/projects/iverilog/) and was created in Lazarus (http://www.lazarus-ide.org/) -
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PipeFitter
Synthesis from Verilog HDL to asynchronous micropipelines
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MatlabSimulink2CPP
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/
