Search Results for "git:/git.code.sf.net/p/docfetcher/code"
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4 projects for "git:/git.code.sf.net/p/docfetcher/code" with 2 filters applied:
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SoftCo: Enterprise Invoice and P2P Automation SoftwareSoftCo Accounts Payable Automation processes all PO and non-PO supplier invoices electronically from capture and matching through to invoice approval and query management. SoftCoAP delivers unparalleled touchless automation by embedding AI across matching, coding, routing, and exception handling to minimize the number of supplier invoices requiring manual intervention. The result is 89% processing savings, supported by a context-aware AI Assistant that helps users understand exceptions, answer questions, and take the right action faster.
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The full-stack observability platform that protects your dataLayer, tags and conversion dataCode-Cube.io detects issues instantly, alerts you in real time and helps you resolve them fast. No manual QA. No unreliable data. Just data you can trust and act on.
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gendasm
Generic Code-Seeking Diassembler with Fuzzy-Function Analyzer
GenDasm is a Generic Code-Seeking Diassembler engine. It allows you to enter known starting vectors for a given code image for the micro. It will disassemble the code and follow through branches to assist in the separation of code and data. Its included Fuzzy Function Analyzer companion uses a DNA Sequence Alignment Algorithm to locate similar code in multiple binaries to facilitate reverse-engineering and/or code recovery. -
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UniSIMD-assembler
SIMD macro assembler unified for ARM, MIPS, PPC and x86
...It establishes a subset of both BASE and SIMD instruction sets with clearly defined common API, so that application logic can be written and maintained in one place without code replication. The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. ... -
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FCML
A machine code manipulation library for Intel 64 and IA-32.
..., SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, AES, TBM, BMI1, BMI2, HLE, ADX, CLMUL, RDRAND, RDSEED, FMA, FMA4, LWP, SVM, XOP, VMX, SMX, AVX-512 Source code moved to: https://github.com/swojtasiak/fcml-lib -
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FlexxCpu
Flexible and eXpandable Cpu simulation
A small simulation of an experimental customized Cpu called FlexxCpu. A virtual Cpu whose assembly instructions have been strongly influenced by old cpus architecture (8080, 6809, z80, 68k, etc...) Please support this project by donating to this fundraiser: ------------------------------------------- Give birth to new travel bicycles!!! https://gofund.me/2201d2a4 ------------------------------------------- -
Securden Privileged Account ManagerDiscover and manage administrator, service, and web app passwords, keys, and identities. Automate management with approval workflows. Centrally control, audit, monitor, and record all access to critical IT assets.
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