Search Results for "intel sse 4.1"

...The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. ...

Fastest Integer Compression. ALL functions are available for AMD/Intel, 64-bit ARMv8 NEON Linux+MacOS/M1 & Power9 Altivec. 100% C (C++ headers), as simple as memcpy. OS:Linux amd64, arm64, Power9, MacOs (Amd/intel + Apple M1).

...- Support for the Intel and AT&T syntax - An instruction renderer - An instruction parser - Instructions represented as generic models - UNIX/GNU/Linux and Windows support - Portable - written entirely in C (no external dependencies) - C++ wrapper - Supported instruction sets: MMX, 3D-Now!, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, AES, TBM, BMI1, BMI2, HLE, ADX, CLMUL, RDRAND, RDSEED, FMA, FMA4, LWP, SVM, XOP, VMX, SMX, AVX-512 Source code moved to: https://github.com/swojtasiak/fcml-lib

A collection of .h macros selected by #defines that support writing C or C++ programs that can be retargeted to Intel SSE, PowerPC, the IBM/Sony CBE, or scalar architectures under recompilation.