Search Results for "/storage/emulated/0/android/data/net.sourceforge.uiq3.fx603p/files" - Page 2
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Showing 113 open source projects for "/storage/emulated/0/android/data/net.sourceforge.uiq3.fx603p/files"
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The AI-powered unified PSA-RMM platform for modern MSPs.SuperOps.ai is the only PSA-RMM platform powered by intelligent automation and thoughtfully crafted for the new-age MSP. The platform also helps MSPs manage their projects, clients, and IT documents from a single place.
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Securden Privileged Account ManagerDiscover and manage administrator, service, and web app passwords, keys, and identities. Automate management with approval workflows. Centrally control, audit, monitor, and record all access to critical IT assets.
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qucs2EQ
Convert Qucs Prv1 data to Audacity EQ curve xml
Convert from Qucs Pr1.v dataset to Audacity equalization curve xml. Tested with Qucs Dataset 0.0.18 and Audacity 2.0.3 -
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Ycad is a library of CAD functions in Java. Currently only DXF is supported for reading, viewing and writing. The DXF drawing may be rendered to a Graphics object for printing or imaging.
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OpenDSE
Open Design Space Exploration Framework
OpenDSE is a design space exploration framework for embedded systems, written in Java. It follows the Y-chart approach where an application consisting of data-dependent tasks is mapped to an architecture consisting of resources. -
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Timing-gen is a Linux tool to generate high quality Postscript timing diagrams from text input files.
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Network Management Software and Tools for Businesses and Organizations | Auvik NetworksReduce IT headaches and save time with a proven solution for automated network discovery, documentation, and performance monitoring. Choose Auvik because you'll see value in minutes, and stay with us to improve your IT for years to come.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
...However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
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dxf2pcb
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags and rounded pads). -
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openCarac
openCarac : Automatize your Spice simulator runnings
openCarac aims to automatize the characterization of electronic circuits using your favourite Spice simulator and provide output files in HTML, LaTeX (c) and GNU Octave (c) scripts. openCarac is natively compatible with various simulators including: - Ngspice (c), http://ngspice.sourceforge.net - Gnucap (c), http://gnucap.org/dokuwiki/doku.php?id=gnucap:start - Xyce (c), http://xyce.sandia.gov It comes with an API which permits to add other features and extend openCarac compatibility; openCarac is also TCL package and comes with functions that can be called in any TCL script. ... -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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Cadence 614 Installer
Cadence 614 installing scripts with source files
this code include automation for installing Cadence614 with Calibre2011 all you need to do is to install Centos 6.5 32bit on your machine http://archive.kernel.org/centos-vault/6.5/isos/i386/CentOS-6.5-i386-LiveCD.iso and the scripts will do the rest -
SoftCo: Enterprise Invoice and P2P Automation SoftwareSoftCo Accounts Payable Automation processes all PO and non-PO supplier invoices electronically from capture and matching through to invoice approval and query management. SoftCoAP delivers unparalleled touchless automation by embedding AI across matching, coding, routing, and exception handling to minimize the number of supplier invoices requiring manual intervention. The result is 89% processing savings, supported by a context-aware AI Assistant that helps users understand exceptions, answer questions, and take the right action faster.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
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This is a collection of (hopefully) useful productivity enhancements of Mentor Graphics IC-Station tools
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Virtual instrumentation software, currently designed for modifying automobile engines. Intended as a modular framework to communicate with devices on an IO port (serial, parallel etc.) and allow a visual representation of the instrument.
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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PCBColorizer
Automatic coloring PCB - make a color circuit board for installation.
The program is designed for automatic coloring schemes of printed circuit boards for ease of installation. For its work requires some files with information on the printed circuit board, package generated by P-CAD. The basic principle: each type of component (identical components) are marked with a unique symbol that has its own color and style. This simplifies the visual search component on the board. The program also generates a text list of components, where the marks, what type of components is associated with which character on the circuit board. -
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PLLSim
Simulation Tool for Phase-Locked Loops
A simulation tool for Phase-Locked Loops with charge pump phase detectors. The tool simulates phase and frequency steps with continous reference and random bit stream reference for data clock recovery. -
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The developed graphical interface is based on the SKILL language which is a Lisp dialect used as a scripting language and PCell (Parameterized Cells) description language used in many EDA software suites by Cadence Design Systems.
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A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
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CAD2Board
is a Qt program to generate SMD chip shooter code
...Any modifications for PCB population can be defined to generate PCB variants, consider rotations from unusual tape and reel packaging or to account in advance for CAD library or PCB design bugs. Generated setup data is stored in a seperate project file. Succeeding PCB revisions what contain redesign changes can be merged with existing project setup data. Inconsistencies are highlighted to solve them by new assignements and unused feeders can be cleaned up with a single push. Finally a machine program is generated in Heeb HE50 format and downloaded to the machine interface. -
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CAPLET
GDS visualization and parallelized capacitance extraction
Project CAPLET is a capacitance extraction toolkit that extract capacitance at field-solver accuracy. CAPLET can directly handle GDS2 layout files into capacitance matrices in both GUI and command line interfaces. The internal extraction algorithm is specialized for VLSI interconnect structures but not exclusively, as long as the structure is of Manhattan geometry and embedded in a uniform dielectric material. -
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HSOC
Heterogeneous System-on-Chip Platform
...Each HSoC component has a clean interface, implements a separate class, and includes regression tests. Large-scale models can be instantiated, by connecting objects from all HSoC libraries. Each object may collect data by invoking a monitoring library. The target users are CS/EE professionals. Some experience with SoC design methodology and SystemC (e.g. reading the SystemC user manual and/or running the examples) is required. To reference this work: M.D. Grammatikakis, A. Papagrigoriou, P. Petrakis, and G. Kornaros, "Monitoring-aware VP prototypeof heterogeneous NoC-based multicore SoCs", Digital System Design Conf. ... -
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The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.
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Web electronic design automation native applications. A set of tools which provides in-browser ability to manipulate data produced by any of gEDA applications.
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Collection of tools for allowing CAD (Computer Aided Design) systems to interact with STEP (ISO 10303) data.
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A Step Closer to a Fully Gui ATLAS .log Converter A Gui .in Editor to be Used by ATLAS .log awk converter
