Open Source Linux Electronic Design Automation (EDA) Software - Page 3

Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.

Wcalc is a tool for the analysis and synthesis of electronic components. Some of the models include coupled microstrip lines, single layer air core solenoid inductors, etc. Wcalc can analyze the electrical parameters based on the physical dimensions a

The ASCO project aims to bring circuit optimization capabilities to existing SPICE simulators using a high-performance parallel differential evolution (DE) optimization algorithm. It supports Eldo, HSPICE, LTspice, Spectre, and Qucs.

An object-oriented Python Interface to Frontline PCB's Genesis 2000 CAD/CAM/CAE system.

ICDPROG is a simple command line programmer for Microchip PIC controllers, using the Microchip ICD (in circuit debugger) as a programmer.

naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information

PCB Layout and Schematic capture tool for Win/Linux/Mac. Source code at https://github.com/sergei-iliev/myNetPCB

Netsim is a mobile ad hoc network simulator targeted at large heterogeneous node configurations. It is written in Java and is easily extensible through its modular concept.

ViPEC is an network analyser for electrical networks. It takes a schematic description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of port parameters (S, Y and Z).

"Magic" VLSI layout tool and various incarnations of the Berkeley tools.

TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.

VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.

InSystem Serial Programmer Fujitsu MCU F2MC-16LX and FR series.

a firmware for AVR910 programmer. started from ver3.8 (http://www.mikrocontroller-projekte.de/Mikrocontroller/AVR-Prog/AVR-Programmer.html) upgraded for speed and reliability. provided generic masterSPI interface please mail me on AlexRainPE196@hotbox.ru

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.

GLogic is a logic gate simulator for linux and an adaptation of the gLogic package....

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support. ipxact2verilog - Generate Verilog module from IP-XACT definition ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component definition verilog2ipxact - Generates IP-XACT definition from Verilog modules vhdl2ipxact - Generates IP-XACT definition from VHDL source ipxactcoherencycheckerverilog / ipxactcoherencycheckervhdl - Validates IP-XACT Component definition with RTL validateipxact - IP-XACT Linting tool

Production (3 level) Programmer for Microchip PIC on Win9X,DOS,NT,Win2K. Flash and Eprom, 14 and 12 bit devices. Printer Port programmers and the BEL In-circuit Dual PRODUCTION Pic Programmer board.

An automatic 2D Delaunay mesh generator and solver for Finite Element Analysis. Can solve 2D field problems (Poisson and Helmholtz Equations). Can use LAPACK/ARPACK solvers producing OpenGL/Postscript output. Uses C/GTK/GTKGLExt/MFC. Runs on Win32/Unix.

Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality. NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox

A Java API for manipulation of GDSII stream data. It is intended to provide a useful, reusable and platform independant library for CAD/CAE application developers. This API Requires the Java Backus-Naur Test API (JBNT). You may download it from: ht

This program contains many tools for you to perform detailed electronic calculations. Ohms, Kirchhoff, Parralel Res., Voltage Divider, Wheatstone, Reistor Color, Zener diode, LED resistor, capacitor, inductor, transformer, capacitive reactance, Transformerless adaptor, R-C Time calculator, Flip-Flop, NE555 calculator, TL431 calculator, 78XX, LM317, Current Limiter, Transistor Regulator, Current Mirror, Battery charge calculations, transistor calculator, mosfet, pass filters, opamp, schmitt-trigger, signal generator, darlington-sziklai, ladder DAC, Long Tailed Pair, Buck-Boost, Logic Gates, Antenna Length, Trace Size, Decibell, Unit Converter, Cable Dia, Electronic Filters, 7 Segment digital, toroid core, smd code, resistor standard finder, heatsink calculator. My Github: https://github.com/shampuan/QTronics-Toolset

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.