Search Results for "git:/git.code.sf.net/p/docfetcher/code" - Page 3

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.

The project has moved! see http://code.google.com/p/kicadocaml/ Kicadocaml is a small project that reads and writes Kicad board (*.brd) files produced by Kicad's pcbnew software. Currently, the software consists of an OpenGL gui & a tool to allow ar

Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.

ODog

Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.

ANVIL - (A)(N)other (V)erilog (I)nteraction (L)evel. C++ and VPI/C code to easily instrument RTL/Verilog (dut) and C++ testbench (tb) for more powerful and efficient verification (i.e., C++/tb drives simulator).

Sk2Py is an wxPython-based IDE which assists in the migration of Cadence Skill(tm)-based PCells to Python PyCells for use in all Open Access environments. Please post any support requests or bug reports to the tracking system.

SIMACH is a Emulator Development Kit. The goal is to develop a IDE that'll allow a developer to easily write and debug a highly portable emulator, automaticly generating code to the destination plataform.

"cif2tribes" is a console-based tool for converting integrated circuit layouts into maps usable in the game Tribes 2, as a 3D visualization aid. The project code is modular enough to be easily extended to different game engines and input file formats.

ESOMA is a component orientated framework for simulation and evaluation of arbitrary microprocessor and DSP architectures. Simulators using ESOMA are runtime configurable. Architectural changes do not need recompiling. Programming language is C++ (Linu

RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.

asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version al

Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.

VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.

cascade is a tool for analyzing the noise and distortion performance for a cascaded system such as the receive path of an RF receiver. The tool is very easy to use and provides a per stage performance summary, a ranking of which elements limit system p

RegMapDef is a project to provide an XML schema and associated tools to support a standardized way of describing register maps. The tools shall incorporate XSL style sheets and scripts to generate documentation, header files, implementation stubs etc.

...UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code which help in finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list. Moreover, the graphical interface lets the user observe the structure of the generated testbench. ...

This program converts assembly code to verilog implementation

NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.