Search Results for "git:/git.code.sf.net/p/docfetcher/code" - Page 3
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Showing 71 open source projects for "git:/git.code.sf.net/p/docfetcher/code"
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Rev Your Digital Product Delivery EnginePlanview links your technology vision directly to teams' daily work, providing complete visibility and control over your digital product delivery ecosystem.
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Endpoint Protection Software for Businesses | HYPERSECUREThe HYPERSECURE endpoint protection platform is a comprehensive suite of products and services enhanced by European third-party solutions. It ensures our customers’ IT security, regulatory compliance, and digital sovereignty.
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An utility which allows schematic capture, board layout and library files conversion from P-CAD to KiCad. --------------------- Old PCadToKiCad utility totally rewritten in C++ and integrated to KiCad itself. This old PCadToKiCad utility is no longer supported. Please, consider using pcad2kicad functionality inside of KiCad project (GOST branch): lp:~kicad-gost-committers/kicad/kicad (https://code.launchpad.net/~kicad-gost-committers/kicad/kicad) Note that lp:kicad branch contains only pcb part of pcad2kicad functionality. ...
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OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
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s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
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The project has moved! see http://code.google.com/p/kicadocaml/ Kicadocaml is a small project that reads and writes Kicad board (*.brd) files produced by Kicad's pcbnew software. Currently, the software consists of an OpenGL gui & a tool to allow ar
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Shoplogix Smart Factory PlatformReal-time Visibility into Your Shop Floor's Performance. The Shoplogix smart factory platform enables manufacturers to increase overall equipment effectiveness, reduce operational costs, sustain growth and improve profitability by allowing them to visualize, integrate and act on production and machine performance in real-time. Manufacturers that trust us to drive efficiency in their factories. Real-time visual data and analytics provide valuable insights to make better informed decisions. Uncover hidden shop floor potential and drive rapid time to value. Develop a continuously improving culture through training, education and data-driven decisions. Compete in the i4.0 world by making the Shoplogix Smart Factory Platform the cornerstone of your digital transformation. Connect to any equipment or device to automate data collection and exchange it with other manufacturing technologies. Automatically monitor, report and analyze machine states to track real-time production.
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SDBoot is a complete bootloader solution (MCU side and PC side), free, with source code for AVR MCU chip. It features a checksumed protocol for safe programming.
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Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.
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ANVIL - (A)(N)other (V)erilog (I)nteraction (L)evel. C++ and VPI/C code to easily instrument RTL/Verilog (dut) and C++ testbench (tb) for more powerful and efficient verification (i.e., C++/tb drives simulator).
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Composable, Open Source Payments PlatformJuspay's Payments Orchestration Platform offers a comprehensive product suite for businesses, including open-source payment orchestration, global payouts, seamless authentication, payment tokenization, fraud & risk management, end-to-end reconciliation, unified payment analytics & more. The company’s offerings also include end-to-end white label payment gateway solutions & real-time payments infrastructure for banks. These solutions help businesses achieve superior conversion rates, reduce fraud, optimize costs, and deliver seamless customer experiences at scale.
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Sk2Py is an wxPython-based IDE which assists in the migration of Cadence Skill(tm)-based PCells to Python PyCells for use in all Open Access environments. Please post any support requests or bug reports to the tracking system.
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SIMACH is a Emulator Development Kit. The goal is to develop a IDE that'll allow a developer to easily write and debug a highly portable emulator, automaticly generating code to the destination plataform.
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"cif2tribes" is a console-based tool for converting integrated circuit layouts into maps usable in the game Tribes 2, as a 3D visualization aid. The project code is modular enough to be easily extended to different game engines and input file formats.
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ESOMA is a component orientated framework for simulation and evaluation of arbitrary microprocessor and DSP architectures. Simulators using ESOMA are runtime configurable. Architectural changes do not need recompiling. Programming language is C++ (Linu
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
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asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version al
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.
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RegMapDef is a project to provide an XML schema and associated tools to support a standardized way of describing register maps. The tools shall incorporate XSL style sheets and scripts to generate documentation, header files, implementation stubs etc.
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UVE
Unified Verification Environment
...UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code which help in finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list. Moreover, the graphical interface lets the user observe the structure of the generated testbench. ... -
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NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.
