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Showing 97 open source projects for "user%20%26%20admin%20panel%20script"
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The full-stack observability platform that protects your dataLayer, tags and conversion dataCode-Cube.io detects issues instantly, alerts you in real time and helps you resolve them fast. No manual QA. No unreliable data. Just data you can trust and act on.
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The AI workplace management platformBy combining AI workflows, predictive intelligence, and automated insights, OfficeSpace gives leaders a complete view of how their spaces are used and how people work. Facilities, IT, HR, and Real Estate teams use OfficeSpace to optimize space utilization, enhance employee experience, and reduce portfolio costs with precision.
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Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.
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Securden Privileged Account ManagerDiscover and manage administrator, service, and web app passwords, keys, and identities. Automate management with approval workflows. Centrally control, audit, monitor, and record all access to critical IT assets.
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A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
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The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research
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OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
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CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms
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A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform
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Get full visibility and control over your tasks and projects with Wrike.Wrike offers world-class features that empower cross-functional, distributed, or growing teams take their projects from the initial request stage all the way to tracking work progress and reporting results.
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Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
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Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.
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VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book
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Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.
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The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.
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libhdlfltp is a VHDL library of floating point operators, all of which are parametrized, synthesizable to FPGAs and cover a number of the core operators in math.h.
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HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
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Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
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This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class.
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This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
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OpenWebServo is an Open Source Hardware and Software project. Its main goal is to develop a web-controlled servo system. The project includes web application, firmware and hardware design.
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Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
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