Showing 10 open source projects for "msc-generator"

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  • 1
    GHDL

    GHDL

    VHDL 2008/93/87 simulator

    ...Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib. GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine.
    Downloads: 81 This Week
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  • 2

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
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  • 3
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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    Downloads: 10 This Week
    Last Update:
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  • 4
    Pulse Programmer
    A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
    Downloads: 3 This Week
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  • Dominate AI Search Results Icon
    Dominate AI Search Results

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  • 5
    CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms
    Downloads: 14 This Week
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  • 6
    A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform
    Downloads: 0 This Week
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  • 7
    Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application
    Downloads: 0 This Week
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  • 8
    This project aims to generate video signal using an FPGA development board
    Downloads: 0 This Week
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  • 9
    System on Chip design generator.
    Downloads: 0 This Week
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    Powerful Business Process Automation

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    When a message is received ThinkAutomation automatically executes one or more Automations. Automations are created using an easy to use drag-and-drop interface to run simple or complex tasks. Automations can perform many business process Actions, including: updating company databases, CRM systems and cloud services, sending outgoing emails, Teams & SMS messages, document processing, custom scripting, integration and much more. Over 100 built-in actions are included, plus ThinkAutomation is extensible with Custom Actions.  
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  • 10
    Tool-independent Makefile generator for VHDL models.
    Downloads: 0 This Week
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