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Verilog processor for Notepad++. Current features:
- Instantiate a module
- Insert registers/wires from a module
- Generate a test bench template
- Automatically inserts a default header for a test bench
- Insert a clocked always block
v1.2.0 now supports ANSI and non-ANSI module declarations.
To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C.
VHDL plugin based on
http://sourceforge.net/projects/nppvhdlplugin/
This version is enhanced to include:
- Insert Instantiation
- Insert Signals
- Create Test Bench Framework
- Insert Component
- Make comments Doxygen compliant
- Create New Behavioral/Structural Entity Template
- Create New Package File Template
- Insert Synchronous Process
- Insert Asynchronous Process
- Insert a Default Header
The default header is set in the vhdlConfig.txt file.
Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )